The present invention relates generally to multi-core chips having a parent core and a scout core, and more specifically, to specific prefetch algorithms for a parent core in a multi-core chip.
Multiple cores may be located on a single chip. In one approach, a second core on the same chip as the parent core may be provided as a scout core. In one approach to leverage or utilize the existing scout core, the scout core is used to prefetch data from a shared cache into the parent core's private cache. This approach may be especially useful in the event the parent core encounters a cache miss. A cache miss occurs when a particular line of data causes a search of a directory of the parent core, and the requested line of cache is not present. One typical approach to obtain the missing cache line is to initiate a fetch operation to a higher level of cache. The scout core provides a mechanism that is used to prefetch data needed by the parent core.
It should be noted that various application behave differently, and as a result one prefetching algorithm or approach may not always improve latency of accessing cache content. Specifically, for example, if the parent core is executing several different applications, then the prefetching algorithm used to monitor the different applications may provide various latencies for accessing cache content depending on the specific application that is being executed. For example, an application designed to search through a sparsely populated database may behave differently (e.g., the prefetching algorithm may provide a higher or lower latency of accessing cache content) when compared to an application designed to perform image color correction.